Digital Logic Project - Signed Multiplication

 Digital Common sense Assignment - Signed Copie Essay



The style tasks of the assignment are to be done in pairs. However , each student must write his/her own VHDL codes, ruse work and submit someone report. Reports must be printed / written NEATLY.


21st January 2010 (Friday, week 13) simply by 4pm. Post to Ms Lee YL (BR4027)

Authorized multiplication can be carried out with either a negative multiplicand or multiplier represented in 2's complement by summation of part product in the multiplicand and the bits of the multiplier except the most important bit (MSB), which is deducted from the partially sum instead. As an example, several × –4 (represented by n=4 bits) are calculated as follows:

0011 Г— 1100:

0 zero 0 00011 Г— 0

0 zero 0 zero 0011 Г— 0

0 0 1 1 +0011 Г— 1

0 zero 1 1 0 zero

0 zero 1 1 –0011 × 1

1 1 you 0 1 0 0(product is –12, represented in 2's complement)

A RISC machine performs the above-described signed integer multiplication of n simply by n parts using a multiplier with the pursuing components:

1 . An n-bit register stores the multiplicand.

2 . An n-bit right-shift register stores the multiplier.

3. A 2n-bit accumulator shift enroll stores the merchandise 4. An n+1-bit 2'complement adder

five. A counter to rely the bits of the multiplier

The types of procedures to perform a 2's match multiply happen to be as follows:

1 . Little counter and product accumulator register will be cleared. installment payments on your Add merchandise of the multiplicand and rightmost bit of multiplier. 3. Move accumulator signup and multiplier register right 1 bit. 4. Decrement counter and repeat via step 2 if count is no more than n – 1 . five. Subtract the item of the multiplicand and little n – 1 of the multiplier.


a) Draw a great ASM graph and or chart for the multiplier

b) Design the datapath.

c) Design the hardwired control unit applying one zehengreifer per express technique. d) Write the VHDL code for your design.